a) Field of the Invention
The present invention relates to a semiconductor storage device, particularly to a high speed dynamic random access memory (DRAM).
b) Description of the Related Art
FIG. 6 is a schematic plan view showing a layout of a conventional DRAM chip.
The DRAM chip 71 has input/output pads 72, column decoders 73, column select signal lines 74, sense amplifiers 75, data bus lines 76, memory cell array blocks 77, word lines 78, and row decoders 79.
As shown in FIG. 6, a plurality of input/output (I/0) pads 72 are disposed in line at the center of the chip 71 in the vertical direction as viewed in FIG. 6. The column decoders CD 73 are disposed near the center of the longer side of the chip 71 in the horizontal direction as viewed in FIG. 6. A column address signal selected by the column decoder 73 is supplied via a column select signal line 74 formed in parallel with the longer side of the chip 71, to the select side (the gate electrode of a column select transistor) of each sense amplifier (S/A) 75. Bit lines BL from each memory cell array block are formed in parallel with column select lines CLS.
Each data bus line 76a for sending an output (information on a selected bit line) at the output side (source of drain electrode of each column select transistor) of each S/A 75 is disposed in parallel with the shorter side of the chip 71, and connected to an output circuit 80 of S/A 75. An amplified signal is supplied via a data bus line 76b to the corresponding I/0 pad 72.
Memory cell array blocks 77, each including memory cells in a matrix shape are disposed on both sides of the train of I/0 pads 72. Bit lines BL 105 connect the memory cells with the input side of S/A 75 and are formed of silicide film. Bit lines 105 extend in parallel with the longer side of the chip 71. Each word line 78 extends in parallel with the shorter side of the chip 71 and connects memory cells with a row decoder RD 79 disposed on either side of the I/0 pads 72.
FIGS. 7A to 7D are cross sectional views explaining the conventional processes of manufacturing a DRAM chip.
Constituent elements of the DRAM chip represented by reference numerals in FIGS. 7A to 7D include a semiconductor Si substrate 81, a field oxide film 82, a source diffusion layer 83, a drain diffusion layer 84, a gate insulating film 85, a gate electrode 86, a storage electrode 87, a capacitor dielectric layer 88, an opposing or common electrode 89, a source diffusion layer 90, a drain diffusion layer 91, a gate insulating film 92, a gate electrode 93, a first SiO.sub.2 film 94, a second SiO.sub.2 film 95, a BPSG film 96, through holes 96a and 96b, a Ti film 97, a TiN film 98, a W film 99, a W plug 99a, an A1 film 100, a word line 100a, a source wiring 100b, a drain wiring 100c, a bit line 105, a TiN film 111, plasma oxide films 112 and 113, a spin-on-glass (SOG) film 114, a plasma oxide film 115, and a via hole 115a.
The conventional processes of manufacturing a DRAM chip will be described with reference to FIGS. 7A to 7D.
First process (refer to FIG. 7A)
Active regions are defined by the field oxide film 82. In one active region, a memory cell constituted by a MOSFET and a storage capacitor is formed, the MOSFET including the source diffusion layer 83, drain diffusion layer 84, gate insulating film 85, gate electrode 86, and source electrode 105 constituting the bit line BL, and the storage capacitor including the storage electrode 87, dielectric layer 88, and opposing electrode 89, respectively formed over the drain diffusion layer 84. In another active region, a peripheral circuit such as a sense amplifier S/A is formed which includes a MOSFET constituted by the source diffusion layer 90, drain diffusion layer 91, gate insulating film 92, and gate electrode 93.
The BPSG film 96 covers the memory cell and the peripheral circuit such as S/A. The first and second SiO.sub.2 films 94 and 95 and the BPSG film 96 in the region of the peripheral circuit such as S/A are selectively etched to form the through holes 96a and 96b exposing the source and drain diffusion layers 90 and 91.
Second process (refer to FIG. 7B )
On the BPSG film 96 with the through holes 96a and 96b formed by the first process, the Ti film 97 is sputtered to a thickness of 20 nm. The TiN film 98 is sputtered on the Ti film 97 to a thickness of 50 nm to be used as a glue layer of the W film 99, to be formed later, for enhancing adhesion to the BPSG film 96.
Next, in order to improve a coverage of the A1 film 100 to be formed by the later sputtering process, the W film 99 is grown on the TiN film 98 to a thickness of 500 nm by chemical vapor deposition (CVD). The W film 99 is etched back to expose the Tin film 98 with a planarized surface and fill the through holes 96a and 96b with the W plug 99a.
Third process (refer to FIG. 7C)
On the TiN film 98 exposed at the second process, the A1 film 100 is sputtered to a thickness of 0.5 .mu.m. The TiN film 112 is sputtered on the A1 film 100 to a thickness of 0.15 .mu.m, and the plasma oxide film 112 is grown on the TiN film 111 to a thickness of 0.1 .mu.m.
Next, the plasma oxide film 112, TiN film 111, A1 film 100, TiN film 98, and Ti film 97 are selectively etched by photolithography (and reactive ion etching (RIE)) to form the word line 100a, source wiring 100b, drain wiring 100c, and data bus line (refer to FIG. 6).
If the TiN film 111 on the A1 film 100 is omitted, a via contact structure to be later formed by A1 wiring directly contacts the A1 film 100. In this case, voids may be generated in the contact surface by A1 migration and a contact defect is likely to occur. A direct contact between two A1 films at a minute region results in a device defect if a void is formed in A1, so that a reliability is greatly deteriorated. In order to avoid this, it is necessary to use a material other than A1 at the minute region in a via hole exposing the A1 film 100. The TiN film 111 is formed on the A1 film 100 from the reason described above.
Since the A1 film 100 is thick, an etching mask function is insufficient if only a resist film is used in photolithography. The plasma oxide film 112 is introduced in order to improve the etching mask function.
The TiN film 111, A1 film 100, TiN film 98, and Ti film 97 all can be etched by the same etching system.
Fourth process (refer to FIG. 7D)
The plasma oxide film (SiO.sub.2) 118 is grown to a thickness of 200 nm on the word line 100a, source wiring 100b, drain wiring 100c, and data bus line (in parallel to the word line, not shown). SOG is coated on the plasma oxide film 113 and cured to form the SOG film 114 filling the trenches between the wiring films. On the SOG film 114, the plasma oxide film (SiO.sub.2) 115 is formed to a thickness of 700 nm. Next, the via hole 115a is formed from the surface of the plasma oxide film 115 to the surface of the TiN layer 111 by photolithography.
With this manufacturing method, however, if the A1 film 100 is made thick in order to reduce the resistance of the data bus line, the spaces between the word lines 100a formed by the A1 film 100 become deep, forming deep and narrow trenches. The pitch of the word lines cannot be widened arbitrarily. Since it is difficult to fill the deep trenches by an easy way such as a TEOS-O.sub.3 oxide film, it becomes necessary to use liquid material such as SOG.
On the plasma oxide film 115, a TiN film is sputtered to a thickness of 100 nm on which film an A1 film is sputtered to a thickness of 800 nm. The A1 film is then patterned by photolithography and RIE to form CLS lines in the same direction as the bit line 105. A semiconductor storage device is thereafter completed by performing other processes such as forming a passivation film.
A DRAM according to a conventional technique explained with FIG. 6 has the following signal paths. (1) external address signal.fwdarw.row decoder 79.fwdarw.selection of word line 78.fwdarw.output of data in memory cells 77 connected to word line 78, to bit lines 105.fwdarw.detection and amplification by S/A 75 of outputs from bit lines 105, (2) external address signal.fwdarw.column decoder 73.fwdarw.column select line 74.fwdarw.selection of S/A 75, and (3) output of data from S/A 75 via data bus line 76.
In a high speed DRAM such as a synchronous dynamic random access memory (SDRAM), all signals are inputted/outputted synchronously with an external clock for the high speed data input/output. The signal paths described above, particularly the data bus line 76 having a long wiring distance and flowing a relatively large current, is required to suppress a signal transmission delay.
In order to suppress the signal transmission delay on the data bus line 76, a low CR constant is required, where C is a capacitance and R is a resistance. It is therefore desired to use a data bus line having a low resistance and a low parasitic capacitance.
The above-described DRAM according to a conventional technique uses basically the word lines and data bus lines disposed in the horizontal direction of the chip, and the CLS lines disposed in the vertical direction.
The word lines and data bus lines disposed in the horizontal direction are required to intersect the CLS lines disposed in the vertical direction in an insulated state, so that two types of lines are formed by using two different wiring layers.
From the above reason, a two-layer structure including first and second wiring layers has been used, the word lines and data bus lines being formed by the first wiring layer, and the CLS lines being formed by the second wiring layer.
it is necessary to form finer word lines as the memory cell size becomes smaller, whereas the resistance of data bus lines is required to be small in order to suppress the signal transmission delay.
in order to form a data bus line of low resistance, it is desired to use low resistance material such as A1 and make a film thick.
However, fine A1 wiring is easily susceptible to electromigration and stress migration. In addition, in order to form a fine and thick wiring layer, a special process of realizing a very high aspect ratio is required.
Furthermore, a parasitic capacitance between adjacent wiring layers increases if they are made fine and thick. For example, interference between word lines may raise the level (potential) of a non-selected word line higher than a ground level (zero potential), destructing data in the non-selected memory cell.
Satisfying both the requirements for fine word lines and low resistance data bus lines is becoming more difficult.